1. Field of the Invention
The present invention relates to word line driver circuits. More particularly, the present invention relates to a circuit and a method for high speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation.
2. Background Information
Conventional volatile and non-volatile memory, devices include an array of memory cells. Memory cells are storage units arranged at the intersections of a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. Memory cells are programmed in the following manner. In a first step, a row address and a column address are supplied to memory cells of a memory chip to select a wordline and to select a bitline respectively. In a second step, from the plurality of word lines, only one word line is selected and the memory cell coupled to the selected word line is driven by a word line driver. In a third step, the bit lines coupled to the selected word line carry the contents of the selected memory cells. In a fourth step, the data in the bitlines are amplified by the sense amplifiers to output the logic data during a read cycle. In a fifth step, during a write cycle, data is forced from the high voltage page latch write drivers to the bit lines into the enabled memory cells. The word line driver circuit is one of the most important circuits in a memory array.
In a conventional memory read operation, all memory circuit voltage levels are low voltage (LV) levels even for the high voltage (HV) memory circuits. However, during HV circuit program/erase operations, LV circuits are biased with low voltage only and HV circuits are biased with high voltage. HV is defined as voltages higher than the normal LV power supply range. In general, LV devices can only support LV levels, but HV devices can support both LV and HV levels. LV devices have lower threshold voltages compared to the HV devices. Also, LV devices have thinner gate oxides than the HV devices. Hence, a LV device has higher drive strength than a HV device for a given device size.
A conventional Bi-gate non-volatile (NV) memory cell comprises a CMOS (Complementary Metal Oxide Semiconductor) select gate and comprises a SONOS (Silicon Oxide Nitride Oxide Silicon) gate, which requires the CMOS select gate to be a high speed gate terminal. As a result, the CMOS select gate is driven with LV higher gain devices like a conventional LV Row Driver.
Referring to FIG. 1, a conventional SONOS memory cell coupled with the wordline driver system 100 is shown, which comprises a LV driver 110. The LV driver 110 is configured as an inverter, which is coupled to a signal word line bar wlb at an input terminal and generates an output signal word line WL. A first NMOS (N-channel Metal Oxide Semiconductor) transistor 120 of the memory cell is coupled to the output signal WL at a gate terminal and a SONOS transistor 122 is coupled to an output signal Word Line SONOS select (WLS) from a HV row switch 130. The NMOS transistor 120 is a select transistor of the memory cell. The first NMOS transistor 120 and the SONOS transistor 122 are coupled in a series configuration of a SONOS memory cell. The SONOS transistor 122 is driven by the HV row switch 130. To improve the program inhibit characteristics of the SONOS memory cell shown in FIG. 1, it is often required to operate the Word Line WL at HV levels during program operations. A disadvantage of the conventional word line driver system 100 is that HV isolation is absent between the LV row driver 110 and Word Line WL. Due to this, WL cannot operate at HV levels, and, hence, better program inhibit characteristics cannot be realized.
Referring to FIG. 2, another conventional SONOS memory cell word line driver 200 is shown, which comprises a HV Level Shifter 210. An input signal row bar (rowb) is coupled to the HV level shifter 210. An output terminal of the HV Level Shifter 210 is coupled to input terminal of a HV row driver 220, wherein the HV row driver is configured as an inverter. The HV level shifter 210 and the HV row driver 220 represent a word line driver circuit. A memory cell select transistor 230 (a first NMOS transistor) is coupled to an output signal word line WL from the HV row driver 220. A SONOS transistor 232, which is coupled in series with the memory cell select transistor 230 is further coupled to a Word Line SONOS select signal (WLS) at its gate terminal. The series combination of the SONOS transistor 232 and the select transistor 230 represents a SONOS memory cell. The Word Line (WL) needs to be driven with LV or HV, and the row driver must now be a HV row driver 220 as shown in FIG. 2, which can also support LV levels. The devices within the HV Row Driver 220 and also the HV Level Shifter 210 are made of p-channel high voltage (PHV) and n-channel high voltage (NHV) devices that can support High Voltage (HV) for a given technology.
During memory read operations, LV input signal row bar (rowb) is high to deselect the Word Line in a low slate. When the signal rowb goes low, the HV Level Shifter 210 and the HV Row Driver 220 operate to bring the Word Line to a high LV state. In the HV memory program operation, to improve the program inhibit characteristics of the memory cell, a high LV row bar rowb input signal is level shifted to HV levels and the HV Row Driver 220 then drives a HV low onto the Word Line. Similarly, a low LV row bar rowb input signal is level shifted and then a HV high signal is driven onto the Word Line. It is to be noted that a high HV signal during memory program operation is the positive power supply of both the HV Level Shifter 210 and Row Driver 220 and is normally higher than the LV power supply. A low HV signal during memory program operation is the low power supply of the HV Level Shifter 210 and Row Driver 220. Moreover, the low HV signal can be lower than ground potential which is the LV power supply low level.
A disadvantage of the word line driver 200 shown in FIG. 2 is that it has slow read speeds due to power Supply headroom issues related to high threshold voltage (VT) of the HV devices. Another disadvantage is slow speed of the HV Level Shifter and the HV Row Driver, and added parasitic loading due to large HV devices. In one application using 130 nm EEPROM and Flash SONOS technology, HV devices with gate oxide thickness (Tox) of 110 Angstorm and drawn channel length (L) of 0.5 um must withstand 11 Volts on the source/drain relative to the bulk and 7.4 Volts on the gate relative to the channel. Normal LV devices in the EEPROM technology have Tox or 32 Angstorm with minimum channel length (L) of 0.15 um. In a conventional solution, since both the Tox and L are inversely proportional to gain and thus speed, the size of HV devices to maintain the speed of LV circuits needs to be approximately 11.5 times larger in width than LV device sizes [˜(110 Angstorm/32 Angstorm)×(0.5 um/0.15 um)] that would normally drive the Word Line. This dimension is impractical especially when considering that the Word Line Drive devices need to be placed on the row pitch of the memory cell. Since the HV Level Shifter and HV Row Driver consist of PHV (P-channel High Voltage) and NHV (N-channel High Voltage) devices with threshold voltages (VT) that can be greater than 60% of the LV power supply range, this conventional circuit is slow due to voltage headroom issues where the gate drive of the PHV and NHV devices is low. Thus, the conventional device speed and functionality are impacted.
Referring to FIG. 3, another conventional SONOS word line driver system 300 is shown, which comprises a LV row driver 310 coupled to transmission gate logic. An input signal row bar (rowb) is coupled to the LV row driver 310, wherein the row driver is configured as an inverter. An output terminal of the LV row driver 310 is coupled to an input terminal of a transmission gate 320. The transmission gate 320 is coupled to a high voltage signal (HV Pass/Iso) at a first control terminal. The second control terminal of the transmission gate 320 is supplied by the inverted version of the high voltage signal HV Pass (may also be referred to as signal Iso). An output terminal of the transmission gate 320 is coupled to a SONOS memory cell 330 and is coupled to a HV Switch 340. The SONOS memory cell 330 comprises a select transistor 332 (a first NMOS transistor), which is coupled to an output signal word line WL. A SONOS transistor 334, which is coupled in series with the select transistor 332, is further coupled to a Word Line SONOS Select signal (WLS) at its gate terminal. In a memory read step, the word line driver system 300 shown in FIG. 3 passes LV signals from LV Row Driver to the Word Line. In a memory programming step, the word line driver system 300 isolates HV levels on WL from the LV Row Driver 310. The Word Line obtains the HV level from the HV Switch 340 that is off during memory read operations. During memory read, the LV input signal row bar (rowb) of deselected rows is high and the output of the LV Row Driver 310 is low, which is passed by the transmission gate 320 to the deselected Word Line. When the signal row bar (rowb) goes to a low LV level, the selected Word Line goes to a high LV level. The transmission gate 320 is in a switched off mode during memory programming. Thus, the LV Row Driver 310 does not see any high voltage. In accordance with an exemplary embodiment of the present invention the word line driver system 300 can be a memory system.
A disadvantage of the conventional SONOS memory cell Word Line Driver 300 shown in FIG. 3 is that of slow read speeds since the transmission gate 320 also suffers from voltage headroom issues due to high threshold voltage (VT) PHV and NHV devices. Since the transmission gate 320 needs to isolate HV in program operations, the devices need to be PHV and NHV devices. Moreover, to maintain speed, the conventional device sizes need to be on the order of approximately 11.5 times (as described earlier) the LV Row Driver size, which is very difficult to fit on the memory cell row pitch. Also, the gates of the PHV and NHV devices of the transmission gate and the HV switch need to have HV gate control signals.
It is desirable to provide a high speed row driver circuit with bootstrapped interface to Word Line (WL) that does not suffer from leakage, speed or power supply headroom limitations.